1. Field of the Invention
The present invention relates to a clock generating circuit used for a semiconductor memory device. More specifically, the present invention relates to a clock generating circuit generating, by a digital DLL (Delay Locked Loop), an internal clock synchronous with an externally applied reference clock, and to a semiconductor memory device provided with the clock generating circuit.
2. Description of the Background Art
For generating a clock signal in a semiconductor memory device, a technique has been known in which a clock generating circuit employing a digital DLL (Delay Lock Looped) (hereinafter also simply referred to as a DLL circuit) is used to delay phase of an externally applied reference clock signal to generate an internal clock signal synchronized with the external clock. This technique is of particular importance in a synchronous semiconductor memory device (SDRAM: Synchronous Dynamic Random Access Memory). Recently, a DDR-SDRAM (Double Data Rate SDRAM) capable of outputting data at the timings of both rising and falling edges of the external clock signal to attain higher speed of operation has been developed.
FIG. 31 is a timing chart representing operation timings of the DDR-SDRAM.
Referring to FIG. 31, reference character ext.CLK represents an external reference clock signal which repeatedly rises and falls at the period of Tc. In the DDR-SDRAM, data DQ is output both at the rising edge and the falling edge of ext.CLK. In order to output data at timings synchronized with ext.CLK, it is necessary to generate in the semiconductor memory device an internal clock pulse int.CLKP as a trigger, at a timing earlier by a data output delay time To consumed by a data output buffer than the timing of rising and falling edges of ext.CLK.
Further, in the DDR-SDRAM, generally, xe2x80x9cSSTL2xe2x80x9d is used as an interface standard for the clock input signal generally. FIG. 32 is a timing chart representing SSTL2 standard.
In STTL2, external clock signal ext.CLK and an inverted signal /ext.CLK thereof as complementary signals are used to define a rising edge of the clock at a timing when signal levels satisfy the condition of ext.CLK greater than /ext.CLK and conversely, the falling edge at the timing when /ext.CLK greater than ext.CLK.
As the data DQ is output in response to the rising and falling edges, the two output periods of data output corresponding to one period of the external clock signal are represented as a period tCH from a rising edge to the falling edge of the clock and a time period tCL from the falling edge to the rising edge. In the DDR-SDRAM, the ratio between tCH and tCL should desirably be 50:50, and SSTL2 standard requires that the ratio is within the range of 55:45 to 45:55.
FIG. 33 is a block diagram representing a configuration of a conventional DDL circuit 1000 used in a synchronous semiconductor memory device.
Referring to FIG. 33, DLL circuit 1000 includes: a clock input buffer 1010 receiving external clock signal ext.CLK and reference voltage Vref and outputting a clock signal BufCLK; a delay circuit 120 receiving clock signal BufCLK, adding a delay time in accordance with a count data ADR less than 0:Mxe2x88x921 greater than  and outputting the result; a level shifter 130 for changing voltage level of an output signal from delay circuit 120; a delay replica circuit 140 adding a prescribed delay time to the output of level shifter 130 and outputting a feedback clock signal FBCLK; and a phase difference control circuit 150 controlling phase difference between feedback clock signal FBCLK and clock signal BufCLK.
FIG. 34 is a circuit diagram representing a configuration of a clock input buffer 1010.
Referring to FIG. 34, clock input buffer 1010 has P type MOS transistors QPa and QPb as well as N type MOS transistors QNa and QNb constituting a current mirror amplifier comparing input voltage levels at input nodes Ni1 and Ni2, amplifying difference between the voltage levels and outputting the difference to node Nb, and an inverter IVa outputting a signal in accordance with the voltage level at node Nb to node No. The clock signal BufCLK is output to node No.
Again referring to FIG. 33, phase difference control circuit 150 includes: a phase comparing circuit 152 comparing phases of clock signal BufCLK and feedback clock signal FBCLK and outputting count designating signals DWN, UP and LCK and a count clock signal cntclk in accordance with the result of comparison; and an up/down count circuit 154 setting the delay control amount count data ADR less than 0:Mxe2x88x921 greater than  in accordance with the count designating signals.
Up/down count circuit 154 updates count data ADR less than 0:Mxe2x88x921 greater than  in order to increase/decrease the delay control amount so that clock signals ext.CLK and FBCLK are synchronized, in accordance with the signal levels of count designating signals DWN, UP and LCK. Count data ADR less than 0:Mxe2x88x921 greater than  is a signal of M (M: natural number) bits representing the counted delay control amount.
In a locked state, feedback clock signal FBCLK is delayed by exactly one period (Tc) from clock signal BufCLK. At this time, feedback clock signal FBCLK has its phase delayed by Tc+Ti (Ti: delay time generated in clock input buffer) from the external clock signal ext.CLK. Similarly, clock signal int.CLKD has its phase delayed by Tcxe2x88x92To (To: delay time generated in output buffer) from the external clock signal.
The clock int.CLKD output from level shifter 130 is transmitted to pulse generating circuit 1060. Pulse generating circuit 1060 outputs internal clock pulse int.CLKP in response to the rising and falling edges of clock signal ext.CLKD.
FIG. 35 is a circuit diagram representing configuration of pulse generating circuit 1060.
Referring to FIG. 35, pulse generating circuit 1060 includes: a one shot pulse generating circuit 1062 generating a one shot pulse in response to a rising edge of clock signal int.CLKD; and a one shot pulse generating circuit 1064 generating a one shot pulse in response to a falling edge of clock
Referring to FIG. 37, delay unit 200-m has clocked inverters CIVa and CIVb operating in response to a control signal R less than m greater than  from decode circuit 210-m. Clocked inverter CIVa operates when the control signal R less than m greater than  is activated (H level), inverts the clock signal BufCLK and outputs the result. Clocked inverter CIVb operates when control signal R less than m greater than  is inactive (L level), inverts an output of the delay unit of the preceding stage and outputs the result.
Delay unit 200-m further includes an inverter IVc. Inverter IVc has an input node connected to output nodes of clocked inverters CIVa and CIVb. An output of inverter IVc is applied to an input node of clocked inverter CIVb in the delay unit 200-(m+1) of the succeeding stage.
Because of this configuration, when the corresponding control signal R less than m greater than  is active, delay unit 200-m delays clock signal BufCLK and transmits it to the delay unit of the succeeding unit, and when the control signal R less than m greater than  is inactive, the delay unit further delays the delay unit input/output signal of the preceding stage and transmits the result to the delay unit of the succeeding stage. The signal output from IVc of delay unit 200-0 is transmitted to a level shifter 130. An input node of CIVb of delay unit 200-n is coupled to the ground voltage.
In the conventional DLL circuit 1000, however, single delay line causes a problem that the interval of generation of the internal clock pulse int.CLKP is not uniform because of variations of characteristics of the transistors constituting the delay unit.
FIG. 38 is a timing chart representing the problem of the DLL circuit 1000 in accordance with the prior art.
Referring to FIG. 38, in response to the rising edge of external clock signal ext.CLK, clock signal BufCLK rises after the lapse of Ti. A delay time corresponding to the count data ADR less than 0:Mxe2x88x921 greater than  is added by delay circuit 120 to clock signal BufCLK.
The signal BufCLKdly represents waveform of that clock signal BufCLK to which the delay time has been added by one delay unit. The delay time added at the rising edge to the clock signal BufCLKdly is represented by T1, and the delay time added at the falling edge is signal int.CLKD. One shot pulse generating circuit 1062 has an odd-number of inverters 1063 for inverting and delaying clock signal int.CLKD, and a logic gate LGa receiving as two inputs the clock signal int.CLKD and an output of inverter group 1063 and outputting a result of AND operation. One shot pulse generating circuit 1064 includes, in addition to the configuration of one shot pulse generating circuit 1062, an inverter IVb for inverting the clock signal int.CLKD.
Pulse generating circuit 1060 further includes a logic operation gate LGc receiving as two inputs the outputs from one shot pulse generating circuits 1062 and 1064 and outputting the result of an OR operation. Logic gate LGc outputs internal clock pulse int.CLKP. Because of this configuration, the internal clock pulse int.CLKP is activated (raised to the H level) in the form of one shot pulse, both at the rising and falling edges of clock signal int.CLKD.
Again referring to FIG. 33, internal clock pulse int.CLKP is transmitted to output buffer 60 and used as an output trigger for the data signal. Considering the delay time To in the output buffer, it is possible to output data at a timing delayed in phase by Tc from external clock signal ext.CLK, that is, the timing synchronized with the external clock signal, by utilizing the internal clock pulse int.CLKP generated based on the clock signal of the locked state.
FIG. 36 is a block diagram representing a configuration of delay circuit 120.
Referring to FIG. 36, delay circuit 120 has 2M delay units 200-0 to 200-n (n=2Mxe2x88x921) connected in series with each other. Decode circuits 210-0 to 210-n are provided corresponding to delay units 200-0 to 200-n, respectively. Decode circuits 210-0 to 210-n output control signals R less than 0 greater than  to R less than n greater than  designating activation of the corresponding delay unit, in response to count data ADR less than 0:Mxe2x88x921 greater than .
FIG. 37 is a circuit diagram representing configuration of the delay unit.
FIG. 37 shows a configuration of mth (m: natural number from 1 to nxe2x88x921) delay unit 200-m. represented as T2.
The rising and falling times of the signal at the clocked inverter will be represented as Tr (CIV) and Tf (CIV), and the rising and falling times of the signal in the inverter will be represented as Tr (V) and Tf (IV). The delay time T1 is represented as a sum of Tf (CIV) and Tr (IV), and delay time T2 is represented as a sum of Tr (CIV) and Tf (IV).
Generally, the ratio of current drivabilities of N and P MOS transistors constituting the inverter and the clocked inverter is not constant because of variations in manufacturing. Further, difference in fan out capability ratio and the like between the inverter and the clocked inverter may result in different rise and fall times in the inverter and the clocked inverter.
From these reasons, generally, the time periods T1 and T2 are not equal to each other. FIG. 38 shows an example in which T1 greater than T2.
In a locked state, clock signal int.CLKD comes to a rising edge at a timing earlier by To from the rising edge of the next external clock signal. At this time, assuming that the delay control amount represented by count data ADR less than 0:Mxe2x88x921 greater than  is xcex1, the phase difference of int.CLKD from BufCLK with respect to the rising edge is xcex1xc2x7T1. The phase difference of int.CLKD from BufCLK with respect to the falling edge is xcex1xc2x7T2.
From the reasons described above, when the delay times T1 and T2 in the delay unit differ, the ratio between the H level period and the L level period of clock signal int.CLKD comes to be much different from 50:50. One shot pulses are generated as clock pulse int.CLKP in response to the rising and falling edges of clock signal int.CLKD.
When pulses as internal clock pulse int.CLKP that are generated in response to the rising edges of the external clock signal are considered, these pulses are generated while maintaining the period Tc of the external clock signal. Therefore, in the internal clock pulse int.CLKP output from DLL circuit 1000 in accordance with the prior art, the ratio between tCH and tCL described with reference to FIG. 32 is not kept uniform. Therefore, when data output takes place in the DDR-SDRAM by using such clock pulses, SSTL2 standard cannot be satisfied, and synchronized data output cannot trigger signal of a data output operation in the output buffer circuit.
The clock generating circuit includes an input buffer circuit generating an internal signal in response to an external clock signal, a delay circuit adding a delay control time to the internal signal, a delay replica circuit adding an input/output delay time generated by the output buffer circuit and the input buffer circuit to an output signal from the delay circuit, a program circuit for setting, in non-volatile manner, the input/output delay time by an external electrical input, a phase difference control circuit setting the delay control time in accordance with the phase difference between the internal signal and an output signal of the delay replica circuit, and a signal generating circuit generating the internal clock signal in response to the output signal from the delay circuit.
According to a still further aspect, the present invention provides a clock generating circuit generating an internal clock signal in synchronization with an external clock signal, including a delay circuit, an input buffer, a phase difference control circuit and a signal generating circuit.
The input buffer generates an internal signal in response to a clock signal external to the circuit. The delay circuit adds a delay control time to the internal signal.
The delay circuit includes a plurality of delay unit circuits connected in series. The delay unit includes a plurality of inverters connected in series. At least one of the inverters includes a first MOS transistor and a first resistance element coupled in series between a first voltage and an output node, and a second MOS transistor and a second resistance element coupled in series between a second voltage and the output node, and the first and second MOS transistors have their gates connected to an input node of the corresponding inverter.
The phase difference control circuit sets the delay control time by setting the number of the plurality of delay unit circuits to be activated, in accordance with the phase difference between the internal signal and an output signal of the delay circuit.
Therefore, an advantage of the present invention is that because of semiconductor memory device operating in synchronization with an external clock signal, including a memory cell array, a control circuit, an output buffer circuit and a clock generating circuit.
The memory cell array has a plurality of memory cells arranged in a matrix of rows and columns. The control circuit controls data access operation to the memory cell. The output buffer circuit outputs read data from the memory cell. The clock generating circuit generates an internal clock signal synchronized with the external clock signal, which will be a trigger signal of a data output operation in the output buffer circuit.
The clock generating circuit includes an input buffer circuit generating an internal signal in response to the external clock signal, a delay circuit adding a delay control time to the internal signal, a phase difference control circuit setting the delay control time in accordance with phase difference between the internal signal and an output signal from the delay circuit, and a signal generating circuit generating the internal clock signal in response to an output signal of the delay circuit. The phase difference control circuit includes a phase difference comparing circuit comparing phase difference between the internal signal and the output signal of the delay circuit, a phase difference count circuit operating in response to an output of the phase difference comparing circuit and changing setting of the delay control time, and a count stopping circuit instructed by the control circuit and stopping operation of the phase difference count circuit in a period when read data is being output from the semiconductor memory device.
According to a still further aspect, the present invention provides a semiconductor memory device operating in synchronization with an external clock signal, including a memory cell array, a control circuit, an output buffer circuit and a clock generating circuit.
The memory cell array has a plurality of memory cells arranged in a matrix of rows and columns. The control circuit controls data access operation to the memory cell. The output buffer circuit outputs read data from the memory cell. The clock generating circuit generates an internal clock signal synchronized with the external clock signal, which will be a be executed at one of the activating edges of the external clock signal.
For example, in the conventional DLL circuit 1000, a delay loop synchronized with the rising edge of the external clock signal is provided, and therefore it is possible to generate clock pulses synchronized with the external clock signal at the rising edges. As to the falling edges, however, it is difficult to obtain clock pulses synchronized with the external clock signal, because of the influence of difference in transmission characteristics between the rising and falling edges in the delay unit.
An object of the present invention is to provide a configuration of a clock generating circuit generating an internal clock synchronous with an externally applied reference clock by means of a digital DLL (Delay Locked Loop) suitable as a clock generating circuit of a semiconductor memory device represented by a DDR-SDRAM, as well as to provide a semiconductor memory device including such a clock generating circuit.
In summary, the present invention provides a clock generating circuit generating an internal clock signal synchronized with an external clock signal, including a first input buffer circuit, a first delay circuit, a phase difference control circuit, a second input buffer circuit, and a second delay circuit signal generating circuit.
The first input buffer circuit generates a first internal signal in response to the external clock signal. The first delay circuit adds a delay control time to the first internal signal. Phase difference control circuit sets the delay control time in accordance with the phase difference between the first internal signal and an output signal of the first delay circuit. The second input buffer circuit generates a second internal signal having its phase inverted from that of the first internal signal, in response to the external clock signal. The second delay circuit adds the delay control time set commonly with the first delay circuit circuit to the second internal signal, under control of the phase difference control circuit. The signal generating circuit generates an internal clock signal in response to output signals of the first and second delay circuits.
According to another aspect, the present invention provides a the delay circuit capable of adding the delay control time common to the inside and the outside of the delay feedback loop input to the phase control circuit, it is possible to obtain an internal clock signal synchronized with both the rising edge and the falling edge of the external clock signal, while maintaining the duty ratio of the external clock signal.
Further, as a clock generating circuit having a DLL loop maintaining the delay control time at a constant value during a period when the read data is being output is provided, the data reading operation of the semiconductor memory device can be executed with higher stability.
Further, as a clock generating circuit having a DLL loop of which input/output delay time can be adjusted and set by external program even after chip molding is provided, a semiconductor memory device can be provided which operates based on the internal clock signal which is more exactly synchronized with the external clock signal.
Further, as temperature dependency of the delay time added by each delay unit is reduced, a clock generating circuit can be provided which can accommodate an external clock signal having low frequency when the temperature is low, by a delay circuit having smaller layout area.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.